The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a metal oxide semiconductor field effect transistor (MOSFET) having a reduced contact resistance and a method of fabricating such a MOSFET.
One trend in modern integrated circuit manufacturing is to produce semiconductor devices, such as field effect transistors (FETs), which are as small as possible. In a typical FET, a source and a drain are formed in an active area of a semiconductor substrate by implanting n-type or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the channel region is a gate electrode. The gate electrode and body are spaced apart by a gate dielectric layer.
Although the fabrication of smaller transistors allows more transistors to be fabricated on a single semiconductor substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degradation effects. For example, the downscaling of a transistor can result in shrinking of the gate pitch as well as a reduction in the area of the source and drain. The decreased area of the source and drain in turn leads to a decreased area for forming a metal semiconductor alloy contact and an overlying conductively filled via contact. For example, with a gate pitch of 80 nm, a gate length of 20 nm, and a spacer width of 15 nm, the source/drain area for the metal semiconductor alloy contact and the overlying conductively filled via contact is only 30 nm.
In conventional scaled FETs, the metal semiconductor alloy contact resistance and the conductively filled via contact-to-metal semiconductor alloy contact resistance are both increasing to an extent that the FET device performance is being substantially degraded.